1. Field of the Invention
The present invention relates to an ATM communication apparatus and, more particularly, to an ATM communication apparatus having a transmission data temporarily storing circuit for each virtual channel (to be referred to as a xe2x80x9cVCxe2x80x9d hereinafter).
2. Description of the Prior Art
FIG. 1 is a block diagram showing a conventional ATM communication apparatus. As shown in FIG. 1, the ATM cell formation/transmission section of a conventional ATM communication apparatus 1 is constituted by a transmission schedule section 8 for selecting a VC to be sent next, a cell formation/transmission control section 6 for receiving information indicating the selected VC from the transmission schedule section 8 and controlling cell transmission of the VC, a transmission parameter storage section 7 for storing information (transmission parameters) required to control cell transmission, a transmission cell formation section 9 for forming a transmission cell, and a transmission data FIFO 10 used to store the transmission cell. The ATM reception/split section of the ATM communication apparatus 1 is constituted by a reception/cell split control section 12 for breaking up and filtering a reception cell to reclaim original information, a reception data FIFO 13 for storing the payload of the reception cell after split, a host bus interface section 5 for transmitting/receiving data to/from a host system including a host CPU 2, a host memory 3, and a host bus 4, and a physical layer device interface section 11 for transmitting/receiving an ATM cell to/from a physical layer device.
The ATM communication apparatus 1 is connected to the host memory 3 and the host CPU 2 through the host bus 4. The host memory 3 stores transmission/reception payload data. For example, the host CPU 2 performs upper layer processing for a transmission/reception payload, outputs a transmission request, and manages the host memory.
FIG. 2 shows the format of the transmission parameter storage section 7 (see FIG. 1) in the conventional ATM communication apparatus 1.
As shown in FIG. 2, with respect to one VC, the transmission parameter storage section 7 stores cell header information 31, cell trailer information 32, a payload storage address 33 in the host memory 3 (the host memory payload storage address 33 indicating the start address in the payload storage area in the host memory 3), and a host memory payload capacity 34 (indicating the number of bytes of the payload stored in the continuous area starting from the payload storage address 33). Although FIG. 2 shows only the storage elements (storage portions) for one VC, similar storage portions exist in the transmission parameter storage section 7 for all the remaining VCs.
As shown in FIG. 1, the conventional ATM communication apparatus 1 includes the following signal lines: a VC number signal line 19, a transmission parameter signal line 20, a DMA start request signal line 21, a payload data signal line 25, a header/trailer data signal line 26, and a cell data signal line 27. Each signal line will be described in detail below with reference to FIG. 1.
The VC number signal line 19 is used by the transmission schedule section 8 to notify the cell formation/transmission control section 6 of a VC number upon determining the VC to be sent next. The transmission parameter signal line 20 is used to exchange transmission parameters between the cell formation/transmission control section 6 and the transmission parameter storage section 7.
The DMA start request signal line 21 is used by the cell formation/transmission control section 6 to notify the host bus interface section 5 of a DMA read address and a DMA read data length so as to start DMA transfer. The payload data signal line 25 is used to send the payload data DMA-read by the host bus interface section 5 to the transmission cell formation section 9.
The header/trailer data signal line 26 is used to send the cell header information 31 and the cell trailer information 32 (see FIG. 2), which are read out from the transmission parameter storage section 7 by the cell formation/transmission control section 6 through the transmission parameter signal line 20, to the transmission cell formation section 9. The cell data signal line 27 is used to store the transmission cell formed by the transmission cell formation section 9 in the transmission data FIFO 10.
FIG. 3 is a flow chart showing the operation of the conventional ATM communication apparatus. The operation of the conventional ATM communication apparatus will be described with reference to FIG. 3, together with FIGS. 1 and 2.
In the conventional ATM communication apparatus, when there is a cell to be transmitted next, the transmission schedule section 8 notifies the cell formation/transmission control section 6 of a VC number for the cell to the cell formation/transmission control section 6 through the VC number signal line 19 (step S1 xe2x80x9cNOTIFY VC NUMBERxe2x80x9d).
Upon reception of the notification of this VC number, the cell formation/transmission control section 6 notifies the host bus interface section 5 of the host memory payload storage address 33 stored as a DMA read address in the transmission parameter storage section 7 and 48 bytes (the value indicated by the host memory payload capacity 34 in the case of the last cell) as a DMA read data length through the DMA start request signal line 21. The cell formation/transmission control section 6 then gives the host bus interface section 5 an instruction to DMA-read the transmission payload corresponding to one cell from the host memory 3.
Upon reception of this instruction, the host bus interface section 5 DMA-reads 1-cell data in one bus cycle when transmission payload corresponding to one cell or more is stored in a continuous address area in the host memory 3, and DMA read can be continuously performed in terms of the structure of the host bus 4.
If the transmission payload is distributed in different address areas in the host memory 3, or DMA read cannot be continuously performed in terms of the structure of the host bus 4, 1-cell data is DMA-read in a plurality of bus cycles. The DMA-read transmission payload is sent to the transmission cell formation section 9, in which the payload, the cell header information 31, and the cell trailer information 32 are wrapped into a cell. This cell is stored in the transmission data FIFO 10.
Transmission VCs are selected by the transmission schedule section 8 in units of cells, and the same VC is not necessarily selected for two cells consecutively. For this reason, DMA read of a transmission payload, transmission cell formation, and write of data in the transmission data FIFO 10 are performed in units of cells (step S2 xe2x80x9cTRANSFER ONE CELLxe2x80x9d).
This operation is performed for the following reason. Assume that the transmission schedule section 8 selects a given VC as a transmission VC. In this case, if the payload data of two or more cells corresponding to the VC is stored in the transmission data FIFO 10, the transmission sequence is disturbed when the transmission schedule section 8 selects another VC as the next transmission VC.
The transmission cell stored in the transmission data FIFO 10 is sent to a physical layer device through the physical layer device interface section 11 (step S3 xe2x80x9cTRANSMIT ONE CELLxe2x80x9d).
The following problems (first and second problems) are posed in the above ATM communication apparatus (to be referred to as the prior art hereinafter).
The first problem is poor transfer efficiency on the host bus (see reference numeral 4 in FIG. 1).
This is because, in the prior art, DMA read of transmission data in unit of cells produces an overhead associated with arbitration for bus access and the like for each DMA read. Assume that the ATM communication apparatus master-reads payload data from the host memory through a PCI bus interface. In this case, at least the time corresponding to two clocks is required as the time required for the ATM communication apparatus to gain bus access (i.e., the time required to set a FRAME # signal at LOW by obtaining a GNT # signal after setting a REQ # signal at LOW). In addition, since at least two clocks are required to receive the data of the first word from the host memory after the ATM communication apparatus outputs an address, the overhead become at least 2+2=4 clocks for each DMA read.
In practice, the bus access time tends to be longer. In addition, a waiting time is generally present in the time interval between the instant at which the ATM communication apparatus outputs an address and the instant at which the data of the first word is received from the host memory. In this case, as the PCI bus between the ATM communication apparatus and the host memory is more congested, and the bus access time is longer, or the reception of payload data from the host memory is delayed more, the first problem becomes more conspicuous.
The second problem is a long delay between cell transmission determination and actual transmission. This is because, a DMA read must always be performed after cell transmission determination (transmission VC determination), and a delay corresponding to an overhead for a DMA read inevitably occurs for each cell.
The second problem becomes more conspicuous as the PCI bus between the ATM communication apparatus and the host memory is congested more, and the bus access time is longer, or the reception of payload data from the host memory is delayed more.
The present invention has been made in consideration of the above situation in the prior art, and has as its object to provide an ATM communication apparatus which can reduce the delay between the instant at which cell transmission is determined and the instant at which a cell is actually transmitted by improving the transfer efficiency of a host bus.
An ATM communication apparatus according to the present invention DMA-reads transmission data corresponding to a plurality of cells into an internal buffer in one bus cycle, and transmits ATM cells by reading out the transmission data from the buffer. More specifically, the ATM communication apparatus incorporates a transmission data temporarily storing section capable of storing/managing transmission data corresponding to a plurality of cells in units of VCs, and a means for DMA,-reading transmission data corresponding to a plurality of cells into the temporarily storing section in one bus cycle.
In order to achieve the above object, according to the principal aspect of the present invention, there is provided an ATM communication apparatus including:
transmission schedule means for determining a virtual channel to be sent;
cell header storage means for storing header information of a transmission cell;
cell trailer storage means for storing trailer information of the transmission cell;
payload read means for reading out payload data from a host memory; and
transmission cell formation means for forming the payload data read out from the host memory, the cell header information, and the cell trailer information into a transmission cell,
the ATM communication apparatus reading out payload data for a given virtual channel from the host memory, when the transmission schedule means determines transmission for the given virtual channel, forming the payload data, cell header information, and cell trailer information into a transmission cell, and transmitting the cell to a physical layer device,
wherein the ATM communication apparatus further comprises:
transmission payload storage means for storing payloads corresponding to a plurality of cells in units of virtual channels;
payload storage location storage means for storing location information of a location in the transmission payload storage means at which each payload is stored; and
stored payload count storage means for storing information indicating that payloads currently stored in an area indicated by the payload storage location corresponds to a specific number of cells,
when the transmission schedule means determines a transmission virtual channel, payload data corresponding to a plurality of cells is read out from the host memory if no payload for the virtual channel is present in the transmission payload storage means, the payload corresponding to a first cell, a corresponding cell header, and a corresponding cell trailer are formed into a transmission cell, and the cell is transmitted to the physical layer device, while payloads corresponding to second and subsequent cells are temporarily stored in the transmission payload storage means, and
when the transmission schedule means determines the virtual channel as a transmission virtual channel afterward, a payload is directly read out from the transmission payload storage means if the payload is stored in the transmission payload storage means, the payload, corresponding header information, and corresponding trailer information are formed into a transmission cell, and the cell is transmitted to the physical layer device.
According to another aspect of the present invention, in the ATM communication apparatus, when the transmission schedule means determines a virtual channel, payload data is newly read out from the host memory and added/stored in the transmission payload storage means even if the number of payloads for the transmission virtual channel which are stored in the transmission payload storage means is not 0 but is not more than a predetermined threshold.
In the ATM communication apparatus according to the present invention, transmission data corresponding to a plurality of cells for a VC to be sent can be DMA-read into the transmission data temporarily storing section in one bus cycle. With respect to the second and subsequent cells, transmission data can be directly read out from the internal buffer without using the host bus.
The present invention therefore has the following effects.
The first effect is improvement in the utilization efficiency of the host bus for the following reason.
According to the present invention, since the ATM communication apparatus incorporates the storage means capable of storing payload data corresponding to a plurality of cells in units of VCs, payload data corresponding to a plurality of cells can be read into the ATM communication apparatus in one bus cycle. This reduces the overhead accompanying data transfer.
Assume that the ATM communication apparatus master-reads payload data from the host memory through a PCI bus interface. In this case, at least a 2-clock time is required as the time required for the ATM communication apparatus to gain bus access (i.e., the time interval between the instant at which the REQ # signal is set at LOW to obtain GNT # and the instant at which the FRAME # signal is output at LOW). In addition, at least 2-clock time is required for the ATM communication apparatus to receive the data of the first word from the host memory after outputting an address. That is, the overhead required corresponds to at least 2+2=4 clocks per DMA read.
Assume that the total time during which payload data corresponding to one cell is output on the bus corresponds to 12 clocks. In the prior art, the time required to read out payload data corresponding to five cells in units of cells corresponds to at least (2+2+12)xc3x975=80 clocks. In the present invention, however, the time required to read out payload data corresponding to five cells in one bus cycle corresponds only 2+2+(12xc3x975)=64 clocks.
In practice, the bus access time is longer than the above time. In addition, a waiting time is generally present in the time interval between the instant at which the ATM communication apparatus outputs an address and the instant at which the data of the first word is received from the host memory. In this case, as the PCI bus between the ATM communication apparatus and the host memory is congested more, and the bus access time is longer, or the reception of payload data from the host memory is delayed more, the effect of improving the utilization efficiency of the host bus in the ATM communication apparatus of the present invention is enhanced.
The second effect is a small delay between the instant at which cell transmission determined and the instant at which a cell is actually transmitted for the following reason.
According to the present invention, the ATM communication apparatus incorporates the storage means capable of storing payload data corresponding to a plurality of cells in units of VCs. Payload data corresponding to the second or subsequent cells is temporarily stored in this storage means. In cell transmission, payloads are read out from the internal storage area without using the bus, thus avoiding a read delay due to the use of the bus.
Consider, for example, a read delay caused when a payload corresponding to one cell is master-read through the PCI bus interface. At least a 2-clock time is required for the ATM communication apparatus to output the FRAME # signal at LOW after GNT # is obtained by setting the REQ xe2x80x3 signal at LOW. In addition, since at least a 2-clock time is required for the ATM communication apparatus to receive the data of the first word from the host memory after outputting an address, at least a 4-clock delay occurs.
In contrast to this, in the present invention, a read of 1-cell data from the payload data storage means in the ATM communication apparatus involves no uncertain factors, i.e., bus access time. Even if, therefore, the apparatus is connected like a PCI bus interface, only a known value of two clocks needs to be taken into consideration.
In practice, the bus access time is longer than the above time. In addition, a waiting time is generally present in the time interval between the instant at which the ATM communication apparatus outputs an address and the instant at which the data of the first word is received from the host memory. In this case, as the PCI bus between the ATM communication apparatus and the host memory is congested more, and the bus access time is longer, or the reception of payload data from the host memory is delayed more, a marked delay reducing effect of the ATM communication apparatus of the present invention can be obtained.
The above and many other objects, features and advantages of the present invention will become manifest to those skilled in the art upon making reference to the following detailed description and accompanying drawings in which preferred embodiments incorporating the principles of the present invention are shown by way of illustrative examples.